JPH0284347U - - Google Patents
Info
- Publication number
- JPH0284347U JPH0284347U JP16410488U JP16410488U JPH0284347U JP H0284347 U JPH0284347 U JP H0284347U JP 16410488 U JP16410488 U JP 16410488U JP 16410488 U JP16410488 U JP 16410488U JP H0284347 U JPH0284347 U JP H0284347U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- bump
- printed board
- bumps
- superimposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16410488U JPH0719165Y2 (ja) | 1988-12-19 | 1988-12-19 | マルチチップ構造 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16410488U JPH0719165Y2 (ja) | 1988-12-19 | 1988-12-19 | マルチチップ構造 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0284347U true JPH0284347U (en]) | 1990-06-29 |
| JPH0719165Y2 JPH0719165Y2 (ja) | 1995-05-01 |
Family
ID=31449420
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16410488U Expired - Lifetime JPH0719165Y2 (ja) | 1988-12-19 | 1988-12-19 | マルチチップ構造 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0719165Y2 (en]) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013110442A (ja) * | 2013-03-11 | 2013-06-06 | Fujitsu Semiconductor Ltd | 半導体装置の製造方法 |
| US8748229B2 (en) | 2008-06-11 | 2014-06-10 | Fujitsu Semiconductor Limited | Manufacturing method including deformation of supporting board to accommodate semiconductor device |
-
1988
- 1988-12-19 JP JP16410488U patent/JPH0719165Y2/ja not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8748229B2 (en) | 2008-06-11 | 2014-06-10 | Fujitsu Semiconductor Limited | Manufacturing method including deformation of supporting board to accommodate semiconductor device |
| JP2013110442A (ja) * | 2013-03-11 | 2013-06-06 | Fujitsu Semiconductor Ltd | 半導体装置の製造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0719165Y2 (ja) | 1995-05-01 |